The VMOS and the VFET are similar in structure - hence both have the V, for the V-groove process (anizotropic etching - they use a special etchant and wafers cut at a specific angle to make the groves). The BIG difference, and you can see it in the picture (I am attaching a cross-section of the VFET to this message) is that the VFET is a junction FET, there is no oxide insulation between the source-drain structure and the gate, and the part between the source and the drain is all one and the same. The principle of operation of these two devices is quite different. A JFET is a 'normally closed switch' - it is impossible to gat more current to flow through it than at Vgs=0. The current flows through a solid piece of doped semiconductor - think of it as a thin stick. The'gate' is a narrow region on the stick with a ring of oposite doped semiconductor - essentially a sort of circular diode. The diode is NEVER biassed forward, this is not what it's for. But when it's reverse biassed, the reverse biassing causes the extra holes and electrons in the respective semiconductor to partially recombine, forming a piece of inert semiconductor - essentially an insulator. The larger the biassing in reverse, the more this effect extends into both pieces. The important part is how it extends into the 'stick' - in effect, the cross-section of the 'stick' reduces and it's resistance increases. Ultimately, at high reverse bias, a 'pinch-off' effect exists (assuming the 'stick' is thin enough for that to happen before breakdown), where the part going through the ring is completely inert and no current flows at all. The principle is very similar to that of a triode vacuum tube. The device is 'normally on'. In a VFET, the V grooves are placed very close to each other, forming very tall and thin spikes. These are used as the 'sticks', with deposited material in the grooves being the 'ring' - just think of the same stick and ring analogy, then put the thing into a press untill it becomes flattened wide, but very thin. Now stack many one on top of the other ans connect in parallel (for better current handling) and hold them so that the current flows vertically - and you have a VFET.
VMOS like all MOS works very differently - two regions of doped semicondictor are at ends of a structure - immagine two shorter sticks doped one way 'glued' end to end by a thin layer of semiconductor of the oposite doping. This is an equivalent of oposed diodes, and will never conduct on it's own. The 'glue' is then oxydised on the outside, which forms a surface boundary layer. The oxide is covered by a conductive ring on the outside, forming a sort of capacitor if you will. The charge in that capacitor 'pulls' oposite carriers to the boundary layer as it is increased, forming a thin layer of effective oposite doping in the 'glue', thus connecting the two 'sticks' electrically. The higher the voltage on the conductive ring, the larger the region under the boundary level, capable of conducting. The trick here, to current handling, is obviously to keep the 'length' of the boundary layer as short as possible, for a given breakdown voltage between the two end sticks (S and D) when we do not want it to conduct. The device is 'normally off' - oposite of the VFET. Again, think of flattening this structure, connecting many in parallel and turning on end so the 'sticks' are vertical, and you get a VMOS - the same V-groove process is used for thi, because the doped regions are formend by diffusion, which alowes the manufacturer to VERY tightly control the depth, so as they diffuse each layer (stick 1, 'glue', stick 2), they can make the 'glue' (=channel) very thin, i.e. short. This has other positive repercussions which I won't go into right now, and some negative.
In both cases, as manufacturers learned to control the length/width of features on the surface better, rather than only depth, the V-groove process was abandoned, because it is very expensive and not very usable for anything else.
